In some integrated circuits, such as non-volatile memory, readout of data from a memory cell can cause emission of infrared light. Although low in power, such emissions can be detected, particularly if integrated over time while the circuit is in operation. Given sensitive equipment and enough time, it may be possible to use these emissions in order to extract the information that is stored in the cell.
U.S. Patent Application Publication 2010/0213878 describes a method and apparatus for reducing optical emissions in an integrated circuit. The integrated circuit is provided with first circuitry having first and second transistors that emit light during a change in state between states of low and high resistance and second circuitry having third transistors that emit light during a change in state. The third transistors are disposed near at least one of the first and second transistors so that light emissions from the third transistors hinder optical detection of a pattern of light emitted by the first and second transistors.
U.S. Pat. No. 7,962,767 describes an integrated circuit having first and second circuitry which are configured to emit light, when undergoing changes in state. The first and second circuitry are operated to change state at the same time so as to hinder optical detection of the light emitted by the first circuitry.
Various types of one-time programmable memory cells are known in the art. For example, U.S. Pat. No. 6,777,757 describes a programmable memory cell comprising a transistor located at the crosspoint of a column bitline and a row wordline. The transistor has its gate formed from the column bitline and its source connected to the row wordline. The memory cell is programmed by applying a voltage potential between the column bitline and the row wordline to produce a programmed region in the substrate underlying the gate of the transistor.
As another example, U.S. Pat. No. 7,511,982 describes a high-speed sensing scheme for a non-volatile memory array. The memory array includes non-volatile memory cells arranged in a complementary bitline configuration, precharge circuits for precharging the bitlines to a first voltage level such as VSS, a reference circuit for applying a reference charge on the reference bitlines of the complementary bitline pairs, and bitline sense amplifiers for sensing a voltage differential between the complementary bitline pairs. A voltage on the data bitline is changed when a programmed non-volatile memory cell connected to an activated wordline couples the wordline voltage to the data bitline.
U.S. Pat. No. 7,812,420 describes a polydiode structure for a photodiode. An integrated circuit device for converting an incident optical signal into an electrical signal comprises a semiconductor substrate, a well region formed inside the semiconductor substrate, a dielectric layer formed over the well region, and a layer of polysilicon for receiving the incident optical signal, formed over the dielectric layer, including a p-type portion, an n-type portion and an undoped portion disposed. between the p-type and n-type portions. The well region is biased to control the layer of polysilicon for providing the electrical signal.